Minimal Backend Implementation

From LLVM

Jump to: navigation, search

[edit] Minimal Backend Implementation proposal

The goal is to use a very simple architecture that can be used for a minimal backend implementation.

Registers:

16 Registers (R0->R15) R0 -> R13: general purpose registers R14 (SP): used as the stack poitner R15 (PC): Program Counter

No flag register: comparison and conditionnal jump are done in a single instruction.

Instruction set: (very close to LLVM instruction set and Selection DAG nodes)

(TBD)

Retrieved from "http://wiki.llvm.org/Minimal_Backend_Implementation"
Personal tools